1 of 10 features ? 10 years minimum data retention in the absence of external power ? data is automatically protected during power loss ? replaces 32k x 8 volatile static ram, eeprom or flash memory ? unlimited write cycles ? low - power cmos ? read and write access times of 100ns ? lithium energy source is electrically disconnected to retain freshness until power is applied for the first time ? optional industrial temperature range of -40 c to +85 c, designated ind ? jedec standard 28 - pin dip package ? powercap module (pcm) package - directly surface - mountable module - replaceable snap - on powercap provides lithium backup battery - standardized pinout for all nonvolatile sram products - detachment feat ure on powercap allows easy removal using a regular screwdriver pin assignment pin description a0 - a14 - address inputs dq0 - dq7 - data in/data out ce - chip enable we - write enable oe - output enable v cc - power (+3.3v) gnd - ground nc - no connect ds1230w 3.3v 256k nonvolatile sram www.maxim - ic.com 13 1 2 3 4 5 6 7 8 9 10 11 12 14 27 28 - pin encapsulated package 740- mil exte nded a7 a5 a3 a2 a1 a0 dq0 dq1 gnd dq2 v cc we a13 a8 a9 a11 oe a10 ce dq7 dq6 dq5 dq3 dq4 28 26 25 24 23 22 21 20 19 18 17 15 16 a12 a6 a4 a14 1 nc 2 3 nc nc nc v cc we oe ce dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 gnd 4 5 6 7 8 9 10 11 12 13 14 15 16 17 nc a14 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 34 nc gnd v bat 34- pin powercap module (pcm) (uses ds9034pc+ or ds9034pci+ powercap) 19 - 563 6 ; rev 11/10 downloaded from: http:///
ds1230w 2 of 10 description the ds1230w 3.3v 256k nonvolatile sram is a 262,144 - bit, fully static, nonvolatile sram organized as 32,768 words by 8 bits. each nv sram has a self - contained lithium energy source and control circuitry, which constantly monitors v cc for an out - of - tolerance condition. when such a condition occurs, the lithium energy source is automatically switched on and writ e protection is unconditionally enabled to prevent data corruption. dip - package ds1230w devices can be used in place of existing 32k x 8 static rams directly conforming to the popular bytewide 28 - pin dip standard. the dip devices also match the pinout of 28256 eeproms, allowing direct substitution while enhancing per formance. ds1230w devices in the powercap module package are directly surface mountable and are normally paired with a ds9034pc powercap to form a complete nonvolatile sram module. there is no limit on th e number of write cycles that can be executed and no additional support circuitry i s required for microprocessor interfacing. read mode the ds1230w executes a read cycle whenever we (write enable) is inactive (high) and ce (chip enable) and oe (output enable) are active (low). the unique address specified by the 15 addres s inputs (a 0 C a 14 ) defines which of the 32,768 bytes of data is to be accessed. valid data will be available to the eight d ata output drivers within t acc (access time) after the last address input signal is stable, providi ng that ce and oe (output enable) access times are also satisfied. if oe and ce access times are not satisfied, then data access must be measured from the later - occurring signal ( ce or oe ) and the limiting parameter is either t co for ce or t oe for oe rather than address access. write mode the ds1230w executes a write cycle whenever the we and ce signals are active (low) after address inputs are stable. the later - occurring falling edge of ce or we will determine the start of the write cycle. the write cycle is terminated by the earlier rising edge of ce or we . all address inputs must be kept valid throughout the write cycle . we must return to the high state for a minimum recovery time (t wr ) before another cycle can be initiated. the oe control signal should be kept inactive (high) during write cycles to avoid bus contention. however, if the output drivers are enabled ( ce and oe active) then we will disable the outputs in t odw from its falling edge. data retention mode the ds1230w provides full functional capability for v cc greater than 3.0 volts and write protects by 2.8 volts. data is maintained in the absence of v cc without any additional support circuitry. the nonvolatile static rams constantly monitor v cc . should the supply voltage decay, the nv srams automatically wri te protect themselves, all inputs become dont care, and all output s become high - impedance. as v cc falls below approximately 2.5 volts, a power switching circuit connec ts the lithium energy source to ram to retain data. during power - up, when v cc rises ab ove approximately 2.5 volts, the power switching circuit connects external v cc to ram and disconnects the lithium energy source. normal ram operation can resume after v cc exceeds 3.0 volts. freshness seal each ds1230w device is shipped from maxim with its lithium energy source disconnected, guaranteeing full energy capacity. when v cc is first applied at a level greater than 3.0 volts, the lithium en ergy source is enabled for battery back - up operation. downloaded from: http:///
ds1230w 3 of 10 packages the ds1230w is available in two packages: 28 - pin dip and 34 - pin powercap module (pcm). the 28 - pin dip integrates a lithium battery, an sram memory and a nonvolatil e control function into a single package with a jedec - standard, 600 - mil dip pinout. the 34 - pin powercap module integr ates sram memory and nonvolatile control into a module base along with conta cts for connection to the lithium battery in the ds9034pc powercap. the powercap module package design allo ws a ds1230w to be surface mounted without subjecting its lithium backup battery to destructive high - temperature reflow soldering. after a ds1230w module base is reflow soldered, a ds9034pc p owercap is snapped on top of the base to form a complete nonvolatile sram module. the ds9034pc i s keyed to prevent improper attachment. ds 1230w module bases and ds9034pc powercaps are ordered separately and shipped in separate containers. see the ds9034pc data sheet for further informatio n. downloaded from: http:///
ds1230w 4 of 10 absolute maximum ratings voltage on any pin relative to ground - 0.3v to +4.6v operating temperature range commercial: 0c to +70c industrial: - 40c to +85c storage temperature range edip - 40c to +85c powercap - 55c to +125c lead temperature (soldering, 10 s) +260c note: edip is wave or hand soldered only. soldering temperature (reflow, powercap) +260c this is a stress rating only and functional operation of the device at these or an y other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum r ating conditions for extended periods of time may affect reliability. recommended dc operating conditions (t a : see note 10) parameter symbol min typ max units notes power supply voltage v cc 3.0 3.3 3.6 v logic 1 v ih 2.2 v cc v logic 0 v il 0.0 0.4 v dc electrical characteristics (t a : see note 10) (v cc = 3.3v 0.3v) parameter symbol min typ max units notes input leakage current i il -1.0 +1.0 a i/o leakage current ce v ih v cc i io -1.0 +1.0 a output current @ 2.2v i oh -1.0 ma output current @ 0.4v i ol 2.0 ma standby current ce =2.2v i ccs1 50 250 a standby current ce =v cc -0.2v i ccs2 30 150 a operating current i cco1 50 ma write protection voltage v tp 2.8 2.9 3.0 v downloaded from: http:///
ds1230w 5 of 10 capacitance (t a = + 25 c) parameter symbol min typ max units notes input capacitance c in 5 10 pf input/output capacitance c i/o 5 10 pf a c electrical characteristics (t a : see note 10) (v cc = 3.3v 0.3v) parameter symbol ds1230w-100 units notes min max read cycle time t rc 100 ns access time t acc 100 ns oe to output valid t oe 50 ns ce to output valid t co 100 ns oe or ce to output active t coe 5 ns 5 output high - z from deselection t od 35 ns 5 output hold from address change t oh 5 ns writ e cycle time t wc 100 ns write pulse width t wp 75 ns 3 address setup time t aw 0 ns write recovery time t wr1 t wr2 5 20 ns ns 12 13 output high - z from we t od w 35 ns 5 output active from we t oew 5 ns 5 data setup time t ds 40 ns 4 data hold time t dh1 t dh2 0 20 ns ns 12 13 downloaded from: http:///
ds1230w 6 of 10 read cycle see note 1 write cycle 1 see notes 2, 3, 4, 6, 7, 8 and 12 downloaded from: http:///
ds1230w 7 of 10 write cycle 2 see notes 2, 3, 4, 6, 7, 8 and 13 power - down/power - up condition downloaded from: http:///
ds1230w 8 of 10 power - down/power - up timing (t a : see note 10) parameter symbol min typ max units notes v cc fail d etect to ce and we inactive t pd 1.5 s 11 v cc slew from v tp to 0v t f 150 s v cc slew from 0v to v tp t r 150 s v cc valid to ce and we inactive t pu 2 ms v cc va lid to end of write protection t rec 125 ms (t a = + 25 c) parameter symbol min typ max units notes expected data retention time t dr 10 years 9 warning: under no circumstance are negative undershoots, of any amplitude, allo wed when device is in battery backup mode. notes: 1. we is high for a read cycle. 2. oe = v ih or v il . if oe = v ih during write cycle, the output buffers remain in a high - impedance state. 3. t wp is specified as the logical and of ce and we . t wp is measured from the latter of ce or we going low to the earlier of ce or we going high. 4. t dh , t ds are measured from the earlier of ce or we going high. 5. these parameters are sampled with a 5 pf load and are not 100% tested. 6. if the ce low transition occurs simultaneously with or latter than the we low transition, the output buffers remain in a high - impedance state during this period. 7. if the ce high tr ansition occurs prior to or simultaneously with the we high transition, the output buffers remain in high - impedance state during this period. 8. if we is low or the we low transition occurs prior t o or simultaneously with the ce low transition, the output buffers remain in a high - impedance state during this period. 9. each ds1230w has a built - in switch that disconnects the lithium source until v cc is first applied by the user. the expected t dr is defined as accumulative time in the absence of v cc starting from the time power is first applied by the user. 10. all ac and dc electrical characteristics are valid over the full operatin g temperature range. for commercial products, this range is 0 c to 70 c. for industrial products (ind), this range is -40 c to +85 c. 11. in a power - down condition the voltage on any pin may not exceed the voltage on v cc . 12. t wr1 and t dh1 are measured from we going high. 13. t wr2 and t dh2 are measured from ce going high. 14. ds1230 modules are recognized by underwriters laborator ies (u l ) under file e99151. downloaded from: http:///
ds1230w 9 of 10 dc test conditions ac test conditions outputs open output load: 100pf + 1ttl gate cycle = 200ns for operating current inp ut pulse levels: 0 to 2.7v all voltages are referenced to ground timing measurement reference levels input: 1.5v output: 1.5v input pulse rise and fall times: 5ns ordering information part temp range supply tolera nce pin - package speed grade (ns) ds1230w-100+ 0c to +70c 3.3v 0.3v 28 740 e d ip 100 DS1230WP-100+ 0c to +70c 3.3v 0.3v 34 powercap* 100 ds1230w-100ind+ - 40c to +85c 3.3v 0.3v 28 740 e d ip 100 DS1230WP-100ind+ - 40c to +85c 3.3v 0.3v 34 powercap* 100 + denotes a lead (pb) - free/rohs - compliant p ackage . * ds9034pc + or ds9034pci + (powercap) required. must be ordered separately. package information for the latest package outline information and land patterns, go to www.maxim - ic.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs sta tus. package type package code outline no. land pattern no. 28 edip mdt28+3 21-0245 34 pcap pc2+4 21-0246 downloaded from: http:///
ds1230w 10 of 10 revision history revision date description pages changed 121907 added the ordering information table ; r emoved the dip module package drawing and dimension table 8 11/10 updated the storage infor mation, soldering temperature, and lead temperature information in the absolute maximum ratings section; removed the - 150 min/max information from the ac electrical characteristics table; updated the ordering information table (removed -150 parts and leade d -10 0 parts); removed the powercap module drawings and updated the package information table 1, 4, 5, 9 downloaded from: http:///
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